/*
 * ESPRSSIF MIT License
 *
 * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
 *
 * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP32 only, in which case,
 * it is free of charge, to any person obtaining a copy of this software and associated
 * documentation files (the "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
 * to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in all copies or
 * substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _PRO_DPORT_REG_H
#define _PRO_DPORT_REG_H

#define PRO_INTR_STATUS_REG_0 (DR_REG_PRODPORT_BASE + 0x00)
#define PRODPORT_INTR_STATUS_0 0xFFFFFFFF
#define PRODPORT_INTR_STATUS_0_S 0

#define PRO_INTR_STATUS_REG_1 (DR_REG_PRODPORT_BASE + 0x04)
#define PRODPORT_INTR_STATUS_1 0xFFFFFFFF
#define PRODPORT_INTR_STATUS_1_S 0

#define PRO_CACHE_CTRL_REG (DR_REG_PRODPORT_BASE + 0x08)
#define PRODPORT_SLAVE_REQ (BIT(27))
#define PRODPORT_SLAVE_REQ_S 27
#define PRODPORT_AHB_SPI_REQ (BIT(26))
#define PRODPORT_AHB_SPI_REQ_S 26
#define PRODPORT_PRO_SLAVE_REQ (BIT(25))
#define PRODPORT_PRO_SLAVE_REQ_S 25
#define PRODPORT_PRO_AHB_SPI_REQ (BIT(24))
#define PRODPORT_PRO_AHB_SPI_REQ_S 24
#define PRODPORT_PRO_CACHE_SEGM_DROM0_SEL 0x0000000F
#define PRODPORT_PRO_CACHE_SEGM_DROM0_SEL_S 20
#define PRODPORT_PRO_CACHE_SEGM_IRAM0_SEL 0x0000000F
#define PRODPORT_PRO_CACHE_SEGM_IRAM0_SEL_S 16
#define PRODPORT_PRO_FLASH_SEGMENT_DROM0_SEL 0x00000003
#define PRODPORT_PRO_FLASH_SEGMENT_DROM0_SEL_S 14
#define PRODPORT_PRO_FLASH_SEGMENT_IRAM0_SEL 0x00000003
#define PRODPORT_PRO_FLASH_SEGMENT_IRAM0_SEL_S 12
#define PRODPORT_PRO_CACHE_SEGM_DROM0_EN (BIT(11))
#define PRODPORT_PRO_CACHE_SEGM_DROM0_EN_S 11
#define PRODPORT_PRO_CACHE_SEGM_IRAM0_EN (BIT(10))
#define PRODPORT_PRO_CACHE_SEGM_IRAM0_EN_S 10
#define PRODPORT_PRO_CACHE_MASK_DROM0 (BIT(9))
#define PRODPORT_PRO_CACHE_MASK_DROM0_S 9
#define PRODPORT_PRO_CACHE_MASK_IRAM0 (BIT(8))
#define PRODPORT_PRO_CACHE_MASK_IRAM0_S 8
#define PRODPORT_PRO_CACHE_LOCK_1_EN (BIT(7))
#define PRODPORT_PRO_CACHE_LOCK_1_EN_S 7
#define PRODPORT_PRO_CACHE_LOCK_0_EN (BIT(6))
#define PRODPORT_PRO_CACHE_LOCK_0_EN_S 6
#define PRODPORT_PRO_CACHE_FLUSH_DONE (BIT(5))
#define PRODPORT_PRO_CACHE_FLUSH_DONE_S 5
#define PRODPORT_PRO_CACHE_FLUSH_ENA (BIT(4))
#define PRODPORT_PRO_CACHE_FLUSH_ENA_S 4
#define PRODPORT_PRO_CACHE_ENABLE (BIT(3))
#define PRODPORT_PRO_CACHE_ENABLE_S 3
#define PRODPORT_PRO_WAY_SEL (BIT(2))
#define PRODPORT_PRO_WAY_SEL_S 2
#define PRODPORT_PRO_IRAM1_CACHE_ENA 0x00000003
#define PRODPORT_PRO_IRAM1_CACHE_ENA_S 0

#define PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_PRODPORT_BASE + 0x0C)
#define PRODPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F
#define PRODPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 20
#define PRODPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F
#define PRODPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 16
#define PRODPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x000003FF
#define PRODPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0

#define PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_PRODPORT_BASE + 0x10)
#define PRODPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F
#define PRODPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 20
#define PRODPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F
#define PRODPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 16
#define PRODPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x000003FF
#define PRODPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0

#define PRO_BOOT_REMAP_CTRL_REG (DR_REG_PRODPORT_BASE + 0x14)
#define PRODPORT_INIT_BOOT_REMAP (BIT(8))
#define PRODPORT_INIT_BOOT_REMAP_S 8
#define PRODPORT_PRO_BOOT_REMAP_FRC 0x00000003
#define PRODPORT_PRO_BOOT_REMAP_FRC_S 0

#define PRO_CPU_PER_CONF_REG (DR_REG_PRODPORT_BASE + 0x18)
#define PRODPORT_FAST_CLK_RTC_SEL (BIT(2))
#define PRODPORT_FAST_CLK_RTC_SEL_S 2
#define PRODPORT_LOWSPEED_CLK_SEL (BIT(1))
#define PRODPORT_LOWSPEED_CLK_SEL_S 1
#define PRODPORT_CPUPERIOD_SEL (BIT(0))
#define PRODPORT_CPUPERIOD_SEL_S 0

#define PRO_MEM_PD_MASK_REG (DR_REG_PRODPORT_BASE + 0x1C)
#define PRODPORT_LSLP_MEM_PD_MASK (BIT(0))
#define PRODPORT_LSLP_MEM_PD_MASK_S 0

#define PRO_IRAM_PD_CTRL_REG (DR_REG_PRODPORT_BASE + 0x20)
#define PRODPORT_APP_IRAM1_PD 0x000000FF
#define PRODPORT_APP_IRAM1_PD_S 24
#define PRODPORT_PRO_IRAM1_PD 0x0000FFFF
#define PRODPORT_PRO_IRAM1_PD_S 8
#define PRODPORT_APP_IRAM0_PD 0x0000000F
#define PRODPORT_APP_IRAM0_PD_S 4
#define PRODPORT_PRO_IRAM0_PD 0x0000000F
#define PRODPORT_PRO_IRAM0_PD_S 0

#define PRO_IRAM_FO_CTRL_REG (DR_REG_PRODPORT_BASE + 0x24)
#define PRODPORT_APP_IRAM1_FO 0x000000FF
#define PRODPORT_APP_IRAM1_FO_S 24
#define PRODPORT_PRO_IRAM1_FO 0x0000FFFF
#define PRODPORT_PRO_IRAM1_FO_S 8
#define PRODPORT_APP_IRAM0_FO 0x0000000F
#define PRODPORT_APP_IRAM0_FO_S 4
#define PRODPORT_PRO_IRAM0_FO 0x0000000F
#define PRODPORT_PRO_IRAM0_FO_S 0

#define PRO_DRAM_PD_FO_REG (DR_REG_PRODPORT_BASE + 0x28)
#define PRODPORT_DRAM_FO 0x0000FFFF
#define PRODPORT_DRAM_FO_S 16
#define PRODPORT_DRAM_PD 0x0000FFFF
#define PRODPORT_DRAM_PD_S 0

#define PRO_IRAM_DRAM_SEL (DR_REG_PRODPORT_BASE + 0x2C)
#define PRODPORT_SHAREMEM_MASK_APPDRAM0 (BIT(22))
#define PRODPORT_SHAREMEM_MASK_APPDRAM0_S 22
#define PRODPORT_SHAREMEM_MASK_PRODRAM0 (BIT(21))
#define PRODPORT_SHAREMEM_MASK_PRODRAM0_S 21
#define PRODPORT_SHAREMEM_MASK_AHB (BIT(20))
#define PRODPORT_SHAREMEM_MASK_AHB_S 20
#define PRODPORT_SHAREMEM_DUMP_MODE 0x00000003
#define PRODPORT_SHAREMEM_DUMP_MODE_S 16
#define PRODPORT_APP_IRAM1_MASK_OPSDRAM1 (BIT(10))
#define PRODPORT_APP_IRAM1_MASK_OPSDRAM1_S 10
#define PRODPORT_APP_IRAM1_MASK_DRAM1 (BIT(9))
#define PRODPORT_APP_IRAM1_MASK_DRAM1_S 9
#define PRODPORT_APP_IRAM1_MASK_IRAM0 (BIT(8))
#define PRODPORT_APP_IRAM1_MASK_IRAM0_S 8
#define PRODPORT_PRO_IRAM1_MASK_OPSDRAM1 (BIT(2))
#define PRODPORT_PRO_IRAM1_MASK_OPSDRAM1_S 2
#define PRODPORT_PRO_IRAM1_MASK_DRAM1 (BIT(1))
#define PRODPORT_PRO_IRAM1_MASK_DRAM1_S 1
#define PRODPORT_PRO_IRAM1_MASK_IRAM0 (BIT(0))
#define PRODPORT_PRO_IRAM1_MASK_IRAM0_S 0

#define PRO_TAG_FO_CTRL_REG (DR_REG_PRODPORT_BASE + 0x30)
#define PRODPORT_APP_CACHE_TAG_FORCE_ON (BIT(8))
#define PRODPORT_APP_CACHE_TAG_FORCE_ON_S 8
#define PRODPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0))
#define PRODPORT_PRO_CACHE_TAG_FORCE_ON_S 0

#define PRO_DRAM_TEST (DR_REG_PRODPORT_BASE + 0x34)
#define PRODPORT_DRAM_CEN_TEST 0x0000FFFF
#define PRODPORT_DRAM_CEN_TEST_S 0

#define PRO_APPCPU_CTRL_REG_A (DR_REG_PRODPORT_BASE + 0x38)
#define PRODPORT_APPCPU_BOOT_REMAP (BIT(12))
#define PRODPORT_APPCPU_BOOT_REMAP_S 12
#define PRODPORT_APPCPU_RUNSTALL (BIT(8))
#define PRODPORT_APPCPU_RUNSTALL_S 8
#define PRODPORT_APPCPU_CLKGATE_EN (BIT(4))
#define PRODPORT_APPCPU_CLKGATE_EN_S 4

#define PRO_APPCPU_CTRL_REG_B (DR_REG_PRODPORT_BASE + 0x3C)
#define PRODPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF
#define PRODPORT_APPCPU_BOOT_ADDR_S 0

#define PRO_APPCPU_CTRL_REG_C (DR_REG_PRODPORT_BASE + 0x40)
#define PRODPORT_APPCPU_RESETTING (BIT(0))
#define PRODPORT_APPCPU_RESETTING_S 0

#define PRO_HOST_INF_SEL (DR_REG_PRODPORT_BASE + 0x44)
#define PRODPORT_LINK_DEVICE_SEL 0x000000FF
#define PRODPORT_LINK_DEVICE_SEL_S 8
#define PRODPORT_PERI_IO_SWAP 0x000000FF
#define PRODPORT_PERI_IO_SWAP_S 0

#define PRO_PERIP_CLK_EN (DR_REG_PRODPORT_BASE + 0x48)
#define PRODPORT_PERIP_CLK_EN 0xFFFFFFFF
#define PRODPORT_PERIP_CLK_EN_S 0

#define PRO_PERIP_RST_EN (DR_REG_PRODPORT_BASE + 0x4C)
#define PRODPORT_PERIP_RST 0xFFFFFFFF
#define PRODPORT_PERIP_RST_S 0

#define PRO_WIFI_CLK_EN (DR_REG_PRODPORT_BASE + 0x50)
#define PRODPORT_WIFI_CLK_EN 0xFFFFFFFF
#define PRODPORT_WIFI_CLK_EN_S 0

#define PRO_WIFI_RST_EN (DR_REG_PRODPORT_BASE + 0x54)
#define PRODPORT_SDIO_RST (BIT(5))
#define PRODPORT_WIFI_RST 0xFFFFFFFF
#define PRODPORT_WIFI_RST_S 0

#define PRO_SLAVE_SPI_CONFIG_REG (DR_REG_PRODPORT_BASE + 0x68)
#define PRODPORT_SPI_ENCRYPT_PATH (BIT(16))
#define PRODPORT_SPI_ENCRYPT_PATH_S 16
#define PRODPORT_SPI_ENCRYPT_ENABLE (BIT(12))
#define PRODPORT_SPI_ENCRYPT_ENABLE_S 12
#define PRODPORT_SPI_DECRYPT_ENABLE (BIT(8))
#define PRODPORT_SPI_DECRYPT_ENABLE_S 8
#define PRODPORT_SLAVE_SPI_MASK_APP (BIT(4))
#define PRODPORT_SLAVE_SPI_MASK_APP_S 4
#define PRODPORT_SLAVE_SPI_MASK_PRO (BIT(0))
#define PRODPORT_SLAVE_SPI_MASK_PRO_S 0

#define PRO_AHB_LITE_MASK_REG (DR_REG_PRODPORT_BASE + 0x6C)
#define PRODPORT_AHB_LITE_MASK_APPDPORT (BIT(10))
#define PRODPORT_AHB_LITE_MASK_APPDPORT_S 10
#define PRODPORT_AHB_LITE_MASK_PRODPORT (BIT(9))
#define PRODPORT_AHB_LITE_MASK_PRODPORT_S 9
#define PRODPORT_AHB_LITE_MASK_SDIO (BIT(8))
#define PRODPORT_AHB_LITE_MASK_SDIO_S 8
#define PRODPORT_AHB_LITE_MASK_APP (BIT(4))
#define PRODPORT_AHB_LITE_MASK_APP_S 4
#define PRODPORT_AHB_LITE_MASK_PRO (BIT(0))
#define PRODPORT_AHB_LITE_MASK_PRO_S 0

#define PRO_INTR_MAP_REG_A (DR_REG_PRODPORT_BASE + 0x70)
#define PRODPORT_INTR_MAP_5 0x0000001F
#define PRODPORT_INTR_MAP_5_S 26
#define PRODPORT_INTR_MAP_4 0x0000001F
#define PRODPORT_INTR_MAP_4_S 21
#define PRODPORT_INTR_MAP_3 0x0000001F
#define PRODPORT_INTR_MAP_3_S 16
#define PRODPORT_INTR_MAP_2 0x0000001F
#define PRODPORT_INTR_MAP_2_S 10
#define PRODPORT_INTR_MAP_1 0x0000001F
#define PRODPORT_INTR_MAP_1_S 5
#define PRODPORT_INTR_MAP_0 0x0000001F
#define PRODPORT_INTR_MAP_0_S 0

#define PRO_INTR_MAP_REG_B (DR_REG_PRODPORT_BASE + 0x74)
#define PRODPORT_INTR_MAP_11 0x0000001F
#define PRODPORT_INTR_MAP_11_S 26
#define PRODPORT_INTR_MAP_10 0x0000001F
#define PRODPORT_INTR_MAP_10_S 21
#define PRODPORT_INTR_MAP_9 0x0000001F
#define PRODPORT_INTR_MAP_9_S 16
#define PRODPORT_INTR_MAP_8 0x0000001F
#define PRODPORT_INTR_MAP_8_S 10
#define PRODPORT_INTR_MAP_7 0x0000001F
#define PRODPORT_INTR_MAP_7_S 5
#define PRODPORT_INTR_MAP_6 0x0000001F
#define PRODPORT_INTR_MAP_6_S 0

#define PRO_INTR_MAP_REG_C (DR_REG_PRODPORT_BASE + 0x78)
#define PRODPORT_INTR_MAP_17 0x0000001F
#define PRODPORT_INTR_MAP_17_S 26
#define PRODPORT_INTR_MAP_16 0x0000001F
#define PRODPORT_INTR_MAP_16_S 21
#define PRODPORT_INTR_MAP_15 0x0000001F
#define PRODPORT_INTR_MAP_15_S 16
#define PRODPORT_INTR_MAP_14 0x0000001F
#define PRODPORT_INTR_MAP_14_S 10
#define PRODPORT_INTR_MAP_13 0x0000001F
#define PRODPORT_INTR_MAP_13_S 5
#define PRODPORT_INTR_MAP_12 0x0000001F
#define PRODPORT_INTR_MAP_12_S 0

#define PRO_INTR_MAP_REG_D (DR_REG_PRODPORT_BASE + 0x7C)
#define PRODPORT_INTR_MAP_23 0x0000001F
#define PRODPORT_INTR_MAP_23_S 26
#define PRODPORT_INTR_MAP_22 0x0000001F
#define PRODPORT_INTR_MAP_22_S 21
#define PRODPORT_INTR_MAP_21 0x0000001F
#define PRODPORT_INTR_MAP_21_S 16
#define PRODPORT_INTR_MAP_20 0x0000001F
#define PRODPORT_INTR_MAP_20_S 10
#define PRODPORT_INTR_MAP_19 0x0000001F
#define PRODPORT_INTR_MAP_19_S 5
#define PRODPORT_INTR_MAP_18 0x0000001F
#define PRODPORT_INTR_MAP_18_S 0

#define PRO_INTR_MAP_REG_E (DR_REG_PRODPORT_BASE + 0x80)
#define PRODPORT_INTR_MAP_29 0x0000001F
#define PRODPORT_INTR_MAP_29_S 26
#define PRODPORT_INTR_MAP_28 0x0000001F
#define PRODPORT_INTR_MAP_28_S 21
#define PRODPORT_INTR_MAP_27 0x0000001F
#define PRODPORT_INTR_MAP_27_S 16
#define PRODPORT_INTR_MAP_26 0x0000001F
#define PRODPORT_INTR_MAP_26_S 10
#define PRODPORT_INTR_MAP_25 0x0000001F
#define PRODPORT_INTR_MAP_25_S 5
#define PRODPORT_INTR_MAP_24 0x0000001F
#define PRODPORT_INTR_MAP_24_S 0

#define PRO_INTR_MAP_REG_F (DR_REG_PRODPORT_BASE + 0x84)
#define PRODPORT_INTR_MAP_35 0x0000001F
#define PRODPORT_INTR_MAP_35_S 26
#define PRODPORT_INTR_MAP_34 0x0000001F
#define PRODPORT_INTR_MAP_34_S 21
#define PRODPORT_INTR_MAP_33 0x0000001F
#define PRODPORT_INTR_MAP_33_S 16
#define PRODPORT_INTR_MAP_32 0x0000001F
#define PRODPORT_INTR_MAP_32_S 10
#define PRODPORT_INTR_MAP_31 0x0000001F
#define PRODPORT_INTR_MAP_31_S 5
#define PRODPORT_INTR_MAP_30 0x0000001F
#define PRODPORT_INTR_MAP_30_S 0

#define PRO_INTR_MAP_REG_G (DR_REG_PRODPORT_BASE + 0x88)
#define PRODPORT_INTR_MAP_41 0x0000001F
#define PRODPORT_INTR_MAP_41_S 26
#define PRODPORT_INTR_MAP_40 0x0000001F
#define PRODPORT_INTR_MAP_40_S 21
#define PRODPORT_INTR_MAP_39 0x0000001F
#define PRODPORT_INTR_MAP_39_S 16
#define PRODPORT_INTR_MAP_38 0x0000001F
#define PRODPORT_INTR_MAP_38_S 10
#define PRODPORT_INTR_MAP_37 0x0000001F
#define PRODPORT_INTR_MAP_37_S 5
#define PRODPORT_INTR_MAP_36 0x0000001F
#define PRODPORT_INTR_MAP_36_S 0

#define PRO_INTR_MAP_REG_H (DR_REG_PRODPORT_BASE + 0x8C)
#define PRODPORT_INTR_MAP_43 0x0000001F
#define PRODPORT_INTR_MAP_43_S 5
#define PRODPORT_INTR_MAP_42 0x0000001F
#define PRODPORT_INTR_MAP_42_S 0

#define PRO_INTRUSION_REG_A (DR_REG_PRODPORT_BASE + 0x90)
#define PRODPORT_INTRUSION_CONFIG 0x0000FFFF
#define PRODPORT_INTRUSION_CONFIG_S 0

#define PRO_INTRUSION_REG_B (DR_REG_PRODPORT_BASE + 0x94)
#define PRODPORT_INTRUSION_CODE_MAX_ADDR 0x0000FFFF
#define PRODPORT_INTRUSION_CODE_MAX_ADDR_S 16
#define PRODPORT_INTRUSION_CODE_MIN_ADDR 0x0000FFFF
#define PRODPORT_INTRUSION_CODE_MIN_ADDR_S 0

#define PRO_INTRUSION_REG_C (DR_REG_PRODPORT_BASE + 0x98)
#define PRODPORT_INTRUSION_CODE_END_ADDR 0x0000FFFF
#define PRODPORT_INTRUSION_CODE_END_ADDR_S 16
#define PRODPORT_INTRUSION_CODE_START_ADDR 0x0000FFFF
#define PRODPORT_INTRUSION_CODE_START_ADDR_S 0

#define PRO_INTRUSION_REG_D (DR_REG_PRODPORT_BASE + 0x9C)
#define PRODPORT_INTRUSION_CLK_SLOW_COUNT 0x00003FFF
#define PRODPORT_INTRUSION_CLK_SLOW_COUNT_S 16
#define PRODPORT_INTRUSION_CLK_FAST_COUNT 0x00003FFF
#define PRODPORT_INTRUSION_CLK_FAST_COUNT_S 0

#define PRO_DPORT_ACCESS_CHECK (DR_REG_PRODPORT_BASE + 0xA0)
#define PRODPORT_DPORT_ACCESS_CHECK_APP (BIT(8))
#define PRODPORT_DPORT_ACCESS_CHECK_APP_S 8
#define PRODPORT_DPORT_ACCESS_CHECK_PRO (BIT(0))
#define PRODPORT_DPORT_ACCESS_CHECK_PRO_S 0

#define PRO_DPORT_APB_MASK0 (DR_REG_PRODPORT_BASE + 0xA4)
#define PRODPORT_PRODPORT_APB_MASK0 0xFFFFFFFF
#define PRODPORT_PRODPORT_APB_MASK0_S 0

#define PRO_DPORT_APB_MASK1 (DR_REG_PRODPORT_BASE + 0xA8)
#define PRODPORT_PRODPORT_APB_MASK1 0xFFFFFFFF
#define PRODPORT_PRODPORT_APB_MASK1_S 0

#define PRO_CACHE_MAP_A (DR_REG_PRODPORT_BASE + 0xAC)
#define PRODPORT_PROCACHE_MAP4 0x0000003F
#define PRODPORT_PROCACHE_MAP4_S 24
#define PRODPORT_PROCACHE_MAP3 0x0000003F
#define PRODPORT_PROCACHE_MAP3_S 18
#define PRODPORT_PROCACHE_MAP2 0x0000003F
#define PRODPORT_PROCACHE_MAP2_S 12
#define PRODPORT_PROCACHE_MAP1 0x0000003F
#define PRODPORT_PROCACHE_MAP1_S 6
#define PRODPORT_PROCACHE_MAP0 0x0000003F
#define PRODPORT_PROCACHE_MAP0_S 0

#define PRO_CACHE_MAP_B (DR_REG_PRODPORT_BASE + 0xB0)
#define PRODPORT_PROCACHE_MAP9 0x0000003F
#define PRODPORT_PROCACHE_MAP9_S 24
#define PRODPORT_PROCACHE_MAP8 0x0000003F
#define PRODPORT_PROCACHE_MAP8_S 18
#define PRODPORT_PROCACHE_MAP7 0x0000003F
#define PRODPORT_PROCACHE_MAP7_S 12
#define PRODPORT_PROCACHE_MAP6 0x0000003F
#define PRODPORT_PROCACHE_MAP6_S 6
#define PRODPORT_PROCACHE_MAP5 0x0000003F
#define PRODPORT_PROCACHE_MAP5_S 0

#define PRO_CACHE_MAP_C (DR_REG_PRODPORT_BASE + 0xB4)
#define PRODPORT_PROCACHE_MAP14 0x0000003F
#define PRODPORT_PROCACHE_MAP14_S 24
#define PRODPORT_PROCACHE_MAP13 0x0000003F
#define PRODPORT_PROCACHE_MAP13_S 18
#define PRODPORT_PROCACHE_MAP12 0x0000003F
#define PRODPORT_PROCACHE_MAP12_S 12
#define PRODPORT_PROCACHE_MAP11 0x0000003F
#define PRODPORT_PROCACHE_MAP11_S 6
#define PRODPORT_PROCACHE_MAP10 0x0000003F
#define PRODPORT_PROCACHE_MAP10_S 0

#define PRO_CACHE_MAP_D (DR_REG_PRODPORT_BASE + 0xB8)
#define PRODPORT_PROCACHE_MAP15 0x0000003F
#define PRODPORT_PROCACHE_MAP15_S 0

#define PRO_DPROT_REG_DATE (DR_REG_PRODPORT_BASE + 0xFC)
#define PRODPORT_PRO_DPORT_DATE 0x0FFFFFFF
#define PRODPORT_PRO_DPORT_DATE_S 0
#define PRODPORT_PRO_DPORT_DATE_VERSION 0x1506110

#endif
